yosys -p 'synth_ice40 -top top -blif buspirate.blif' buspirate.v /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8+383 (git sha1 32ff37bb, clang 7.0.0-3 -fPIC -Os) -- Parsing `buspirate.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: buspirate.v Parsing Verilog input from `buspirate.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (iobufphy.v:24) Warning: Yosys has only limited support for tri-state logic at the moment. (iobufphy.v:27) Generating RTLIL representation for module `\iobuf'. Generating RTLIL representation for module `\iobufphy'. Generating RTLIL representation for module `\pwm'. Generating RTLIL representation for module `\spimaster'. Generating RTLIL representation for module `\fifo'. Generating RTLIL representation for module `\sync'. Generating RTLIL representation for module `\top'. buspirate.v:117: Warning: Identifier `\out_fifo_out_pop' is implicitly declared. Successfully finished Verilog frontend. -- Running command `synth_ice40 -top top -blif buspirate.blif' -- 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sync Used module: \iobuf Used module: \fifo Used module: \spimaster Used module: \pwm 2.2.2. Analyzing design hierarchy.. Top module: \top Used module: \sync Used module: \iobuf Used module: \fifo Used module: \spimaster Used module: \pwm Removing unused module `\iobufphy'. Removed 1 unused modules. Mapping positional arguments of cell top.MC_OE_SYNC (sync). Mapping positional arguments of cell top.MC_WE_SYNC (sync). Mapping positional arguments of cell top.AUX_BUF (iobuf). Mapping positional arguments of cell top.CS_BUF (iobuf). Mapping positional arguments of cell top.MISO_BUF (iobuf). Mapping positional arguments of cell top.CLOCK_BUF (iobuf). Mapping positional arguments of cell top.MOSI_BUF (iobuf). Mapping positional arguments of cell top.SPI_MASTER (spimaster). Mapping positional arguments of cell top.AUX_PWM (pwm). Warning: Resizing cell port top.FIFO_OUT.out_data from 16 bits to 8 bits. Warning: Resizing cell port top.FIFO_IN.in_data from 16 bits to 8 bits. 2.3. Executing PROC pass (convert processes to netlists). 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$buspirate.v:143$96 in module top. Marked 2 switch rules as full_case in process $proc$fifo.v:55$58 in module fifo. Marked 4 switch rules as full_case in process $proc$spimaster.v:54$28 in module spimaster. Marked 6 switch rules as full_case in process $proc$pwm.v:34$20 in module pwm. Removed a total of 0 dead cases. 2.3.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\sync.$proc$synchronizer.v:10$79'. Set init value: \r3 = 1'0 Set init value: \r1 = 1'0 Set init value: \r2 = 1'0 Found init rule in `\fifo.$proc$fifo.v:53$75'. Set init value: \out_data_d = 8'00000000 Found init rule in `\fifo.$proc$fifo.v:45$74'. Set init value: \out_pos = 2'00 Found init rule in `\fifo.$proc$fifo.v:44$73'. Set init value: \in_pos = 2'00 Found init rule in `\fifo.$proc$fifo.v:38$72'. Set init value: \in_full = 1'0 Set init value: \in_nempty = 1'0 Set init value: \out_nempty = 1'0 2.3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \rst in `\spimaster.$proc$spimaster.v:54$28'. Found async reset \rst in `\pwm.$proc$pwm.v:34$20'. 2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top.$proc$buspirate.v:143$96'. 1/5: $0\out_fifo_in_shift[0:0] 2/5: $0\spi_state_last[0:0] 3/5: $0\pwm_off[15:0] 4/5: $0\pwm_on[15:0] 5/5: $0\mc_dout_reg[15:0] Creating decoders for process `\sync.$proc$synchronizer.v:10$79'. 1/3: $1\r3[0:0] 2/3: $1\r2[0:0] 3/3: $1\r1[0:0] Creating decoders for process `\sync.$proc$synchronizer.v:16$76'. 1/3: $0\r3[0:0] 2/3: $0\r2[0:0] 3/3: $0\r1[0:0] Creating decoders for process `\fifo.$proc$fifo.v:53$75'. 1/1: $1\out_data_d[7:0] Creating decoders for process `\fifo.$proc$fifo.v:45$74'. 1/1: $1\out_pos[1:0] Creating decoders for process `\fifo.$proc$fifo.v:44$73'. 1/1: $1\in_pos[1:0] Creating decoders for process `\fifo.$proc$fifo.v:38$72'. 1/3: $1\out_nempty[0:0] 2/3: $1\in_nempty[0:0] 3/3: $1\in_full[0:0] Creating decoders for process `\fifo.$proc$fifo.v:55$58'. 1/9: $0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 2/9: $0$memwr$\memory$fifo.v:58$48_DATA[7:0]$60 3/9: $0$memwr$\memory$fifo.v:58$48_ADDR[1:0]$59 4/9: $0\out_data_d[7:0] 5/9: $0\out_pos[1:0] 6/9: $0\in_pos[1:0] 7/9: $0\out_nempty[0:0] 8/9: $0\in_nempty[0:0] 9/9: $0\in_full[0:0] Creating decoders for process `\spimaster.$proc$spimaster.v:54$28'. 1/14: $0\data_o[7:0] [7] 2/14: $0\data_o[7:0] [6] 3/14: $0\data_o[7:0] [5] 4/14: $0\data_o[7:0] [4] 5/14: $0\data_o[7:0] [3] 6/14: $0\data_o[7:0] [2] 7/14: $0\data_o[7:0] [1] 8/14: $0\data_o[7:0] [0] 9/14: $0\bitcount[4:0] 10/14: $0\cs[0:0] 11/14: $0\sclk[0:0] 12/14: $0\mosi[0:0] 13/14: $0\clockphase[0:0] 14/14: $0\state[0:0] Creating decoders for process `\pwm.$proc$pwm.v:34$20'. 1/16: $4\clkout[0:0] 2/16: $6\count[15:0] 3/16: $3\clkout[0:0] 4/16: $5\count[15:0] 5/16: $2\clkout[0:0] 6/16: $4\count[15:0] 7/16: $3\count[15:0] 8/16: $2\count[15:0] 9/16: $1\clkout[0:0] 10/16: $1\count[15:0] 11/16: $1\lastoffperiod[15:0] 12/16: $1\lastonperiod[15:0] 13/16: $0\clkout[0:0] 14/16: $0\lastoffperiod[15:0] 15/16: $0\lastonperiod[15:0] 16/16: $0\count[15:0] 2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top.\mc_dout_reg' using process `\top.$proc$buspirate.v:143$96'. created $dff cell `$procdff$422' with positive edge clock. Creating register for signal `\top.\pwm_on' using process `\top.$proc$buspirate.v:143$96'. created $dff cell `$procdff$423' with positive edge clock. Creating register for signal `\top.\pwm_off' using process `\top.$proc$buspirate.v:143$96'. created $dff cell `$procdff$424' with positive edge clock. Creating register for signal `\top.\spi_state_last' using process `\top.$proc$buspirate.v:143$96'. created $dff cell `$procdff$425' with positive edge clock. Creating register for signal `\top.\out_fifo_in_shift' using process `\top.$proc$buspirate.v:143$96'. created $dff cell `$procdff$426' with positive edge clock. Creating register for signal `\sync.\r3' using process `\sync.$proc$synchronizer.v:16$76'. created $dff cell `$procdff$427' with positive edge clock. Creating register for signal `\sync.\r1' using process `\sync.$proc$synchronizer.v:16$76'. created $dff cell `$procdff$428' with positive edge clock. Creating register for signal `\sync.\r2' using process `\sync.$proc$synchronizer.v:16$76'. created $dff cell `$procdff$429' with positive edge clock. Creating register for signal `\fifo.\in_full' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$430' with positive edge clock. Creating register for signal `\fifo.\in_nempty' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$431' with positive edge clock. Creating register for signal `\fifo.\out_nempty' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$432' with positive edge clock. Creating register for signal `\fifo.\in_pos' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$433' with positive edge clock. Creating register for signal `\fifo.\out_pos' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$434' with positive edge clock. Creating register for signal `\fifo.\out_data_d' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$435' with positive edge clock. Creating register for signal `\fifo.$memwr$\memory$fifo.v:58$48_ADDR' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$436' with positive edge clock. Creating register for signal `\fifo.$memwr$\memory$fifo.v:58$48_DATA' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$437' with positive edge clock. Creating register for signal `\fifo.$memwr$\memory$fifo.v:58$48_EN' using process `\fifo.$proc$fifo.v:55$58'. created $dff cell `$procdff$438' with positive edge clock. Creating register for signal `\spimaster.\state' using process `\spimaster.$proc$spimaster.v:54$28'. created $adff cell `$procdff$439' with positive edge clock and positive level reset. Creating register for signal `\spimaster.\data_o' using process `\spimaster.$proc$spimaster.v:54$28'. created $adff cell `$procdff$440' with positive edge clock and positive level reset. Creating register for signal `\spimaster.\mosi' using process `\spimaster.$proc$spimaster.v:54$28'. created $adff cell `$procdff$441' with positive edge clock and positive level reset. Creating register for signal `\spimaster.\sclk' using process `\spimaster.$proc$spimaster.v:54$28'. created $adff cell `$procdff$442' with positive edge clock and positive level reset. Creating register for signal `\spimaster.\cs' using process `\spimaster.$proc$spimaster.v:54$28'. created $adff cell `$procdff$443' with positive edge clock and positive level reset. Creating register for signal `\spimaster.\bitcount' using process `\spimaster.$proc$spimaster.v:54$28'. created $dff cell `$procdff$444' with positive edge clock. Creating register for signal `\spimaster.\clockphase' using process `\spimaster.$proc$spimaster.v:54$28'. created $dff cell `$procdff$445' with positive edge clock. Creating register for signal `\pwm.\count' using process `\pwm.$proc$pwm.v:34$20'. created $adff cell `$procdff$446' with positive edge clock and positive level reset. Creating register for signal `\pwm.\lastonperiod' using process `\pwm.$proc$pwm.v:34$20'. created $dff cell `$procdff$447' with positive edge clock. Creating register for signal `\pwm.\lastoffperiod' using process `\pwm.$proc$pwm.v:34$20'. created $dff cell `$procdff$448' with positive edge clock. Creating register for signal `\pwm.\clkout' using process `\pwm.$proc$pwm.v:34$20'. created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 4 empty switches in `\top.$proc$buspirate.v:143$96'. Removing empty process `top.$proc$buspirate.v:143$96'. Removing empty process `sync.$proc$synchronizer.v:10$79'. Removing empty process `sync.$proc$synchronizer.v:16$76'. Removing empty process `fifo.$proc$fifo.v:53$75'. Removing empty process `fifo.$proc$fifo.v:45$74'. Removing empty process `fifo.$proc$fifo.v:44$73'. Removing empty process `fifo.$proc$fifo.v:38$72'. Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:55$58'. Removing empty process `fifo.$proc$fifo.v:55$58'. Found and cleaned up 11 empty switches in `\spimaster.$proc$spimaster.v:54$28'. Removing empty process `spimaster.$proc$spimaster.v:54$28'. Found and cleaned up 5 empty switches in `\pwm.$proc$pwm.v:34$20'. Removing empty process `pwm.$proc$pwm.v:34$20'. Cleaned up 22 empty switches. 2.4. Executing FLATTEN pass (flatten design). Using template pwm for cells of type pwm. Using template fifo for cells of type fifo. Using template iobuf for cells of type iobuf. Using template spimaster for cells of type spimaster. Using template sync for cells of type sync. No more expansions possible. Deleting now unused module sync. Deleting now unused module fifo. Deleting now unused module spimaster. Deleting now unused module pwm. Deleting now unused module iobuf. 2.5. Executing TRIBUF pass. 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 306 unused wires. 2.9. Executing CHECK pass (checking for obvious problems). checking module top.. Warning: Wire top.\sram_clock is used but has no driver. Warning: Wire top.\sram1_cs is used but has no driver. Warning: Wire top.\sram0_cs is used but has no driver. Warning: Wire top.\lat_oe is used but has no driver. Warning: Wire top.\irq1_dir is used but has no driver. Warning: Wire top.\irq1_out is used but has no driver. Warning: Wire top.\irq0_dir is used but has no driver. Warning: Wire top.\irq0_out is used but has no driver. found and reported 8 problems. 2.10. Executing OPT pass (performing simple optimizations). 2.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 26 cells. 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $techmap\AUX_PWM.$procmux$387: \AUX_PWM.clkout -> 1'1 Replacing known input bits on port A of cell $techmap\AUX_PWM.$procmux$400: \AUX_PWM.clkout -> 1'0 Analyzing evaluation results. dead port 2/2 on $mux $techmap\AUX_PWM.$procmux$390. dead port 2/2 on $mux $techmap\AUX_PWM.$procmux$396. dead port 1/2 on $mux $techmap\AUX_PWM.$procmux$402. dead port 1/2 on $mux $techmap\AUX_PWM.$procmux$408. Removed 4 multiplexer ports. 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $techmap\FIFO_IN.$procmux$136: Old ports: A=8'00000000, B=8'11111111, Y=$techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 New ports: A=1'0, B=1'1, Y=$techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] New connections: $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [7:1] = { $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_IN.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] } Consolidated identical input bits for $mux cell $techmap\FIFO_OUT.$procmux$136: Old ports: A=8'00000000, B=8'11111111, Y=$techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 New ports: A=1'0, B=1'1, Y=$techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] New connections: $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [7:1] = { $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] $techmap\FIFO_OUT.$0$memwr$\memory$fifo.v:58$48_EN[7:0]$61 [0] } Optimizing cells in module \top. Performed a total of 2 changes. 2.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 1 cells. 2.10.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 337 unused wires. 2.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.10.13. Executing OPT_RMDFF pass (remove dff with constant values). 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 337 unused wires. 2.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.10.16. Finished OPT passes. (There is nothing left to do.) 2.11. Executing WREDUCE pass (reducing word size of cells). Removed top 5 bits (of 6) from port B of cell top.$eqx$buspirate.v:133$81 ($eqx). Removed top 1 bits (of 6) from port B of cell top.$eqx$buspirate.v:140$93 ($eqx). Removed top 1 bits (of 6) from port B of cell top.$procmux$124_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$procmux$118_CMP0 ($eq). Removed top 7 bits (of 8) from FF cell top.$techmap\FIFO_IN.$procdff$438 ($dff). Removed cell top.$techmap\FIFO_IN.$procmux$142 ($mux). Removed cell top.$techmap\FIFO_IN.$procmux$139 ($mux). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_IN.$ternary$fifo.v:52$57 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_IN.$add$fifo.v:52$56 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_IN.$add$fifo.v:52$56 ($add). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_IN.$ternary$fifo.v:50$54 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_IN.$add$fifo.v:50$53 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_IN.$add$fifo.v:50$53 ($add). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_IN.$ternary$fifo.v:49$51 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_IN.$add$fifo.v:49$50 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_IN.$add$fifo.v:49$50 ($add). Removed top 31 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$290_CMP0 ($eq). Removed top 30 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$264_CMP0 ($eq). Removed top 30 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$240_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$218_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$198_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$180_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$procmux$164_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$techmap\SPI_MASTER.$sub$spimaster.v:105$45 ($sub). Removed top 7 bits (of 8) from FF cell top.$techmap\FIFO_OUT.$procdff$438 ($dff). Removed cell top.$techmap\FIFO_OUT.$procmux$142 ($mux). Removed cell top.$techmap\FIFO_OUT.$procmux$139 ($mux). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_OUT.$ternary$fifo.v:52$57 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_OUT.$add$fifo.v:52$56 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_OUT.$add$fifo.v:52$56 ($add). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_OUT.$ternary$fifo.v:50$54 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_OUT.$add$fifo.v:50$53 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_OUT.$add$fifo.v:50$53 ($add). Removed top 30 bits (of 32) from mux cell top.$techmap\FIFO_OUT.$ternary$fifo.v:49$51 ($mux). Removed top 31 bits (of 32) from port B of cell top.$techmap\FIFO_OUT.$add$fifo.v:49$50 ($add). Removed top 30 bits (of 32) from port Y of cell top.$techmap\FIFO_OUT.$add$fifo.v:49$50 ($add). Removed top 30 bits (of 32) from wire top.$techmap\FIFO_IN.$add$fifo.v:49$50_Y. Removed top 30 bits (of 32) from wire top.$techmap\FIFO_IN.$add$fifo.v:50$53_Y. Removed top 30 bits (of 32) from wire top.$techmap\FIFO_OUT.$add$fifo.v:49$50_Y. Removed top 30 bits (of 32) from wire top.$techmap\FIFO_OUT.$add$fifo.v:50$53_Y. 2.12. Executing SHARE pass (SAT-based resource sharing). Found 2 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $techmap\FIFO_OUT.$memrd$\memory$fifo.v:68$68 ($memrd): Found 1 activation_patterns using ctrl signal $techmap\FIFO_OUT.$logic_and$fifo.v:67$67_Y. No candidates found. Analyzing resource sharing options for $techmap\FIFO_IN.$memrd$\memory$fifo.v:68$68 ($memrd): Found 1 activation_patterns using ctrl signal $logic_and$buspirate.v:135$85_Y. No candidates found. 2.13. Executing TECHMAP pass (map to technology primitives). 2.13.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.13.2. Continuing TECHMAP pass. Using template $paramod$0760830c1e6c196382cd2cb153e9fff2d84c061d\_90_lut_cmp_ for cells of type $eq. No more expansions possible. 2.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 369 unused wires. 2.16. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $techmap\AUX_PWM.$add$pwm.v:59$25 ($add). creating $macc model for $techmap\FIFO_IN.$add$fifo.v:49$50 ($add). creating $macc model for $techmap\FIFO_IN.$add$fifo.v:50$53 ($add). creating $macc model for $techmap\FIFO_IN.$add$fifo.v:52$56 ($add). creating $macc model for $techmap\FIFO_OUT.$add$fifo.v:49$50 ($add). creating $macc model for $techmap\FIFO_OUT.$add$fifo.v:50$53 ($add). creating $macc model for $techmap\FIFO_OUT.$add$fifo.v:52$56 ($add). creating $macc model for $techmap\SPI_MASTER.$sub$spimaster.v:105$45 ($sub). creating $alu model for $macc $techmap\SPI_MASTER.$sub$spimaster.v:105$45. creating $alu model for $macc $techmap\FIFO_OUT.$add$fifo.v:52$56. creating $alu model for $macc $techmap\FIFO_OUT.$add$fifo.v:50$53. creating $alu model for $macc $techmap\FIFO_OUT.$add$fifo.v:49$50. creating $alu model for $macc $techmap\FIFO_IN.$add$fifo.v:52$56. creating $alu model for $macc $techmap\FIFO_IN.$add$fifo.v:50$53. creating $alu model for $macc $techmap\FIFO_IN.$add$fifo.v:49$50. creating $alu model for $macc $techmap\AUX_PWM.$add$pwm.v:59$25. creating $alu cell for $techmap\AUX_PWM.$add$pwm.v:59$25: $auto$alumacc.cc:474:replace_alu$461 creating $alu cell for $techmap\FIFO_IN.$add$fifo.v:49$50: $auto$alumacc.cc:474:replace_alu$464 creating $alu cell for $techmap\FIFO_IN.$add$fifo.v:50$53: $auto$alumacc.cc:474:replace_alu$467 creating $alu cell for $techmap\FIFO_IN.$add$fifo.v:52$56: $auto$alumacc.cc:474:replace_alu$470 creating $alu cell for $techmap\FIFO_OUT.$add$fifo.v:49$50: $auto$alumacc.cc:474:replace_alu$473 creating $alu cell for $techmap\FIFO_OUT.$add$fifo.v:50$53: $auto$alumacc.cc:474:replace_alu$476 creating $alu cell for $techmap\FIFO_OUT.$add$fifo.v:52$56: $auto$alumacc.cc:474:replace_alu$479 creating $alu cell for $techmap\SPI_MASTER.$sub$spimaster.v:105$45: $auto$alumacc.cc:474:replace_alu$482 created 8 $alu and 0 $macc cells. 2.17. Executing OPT pass (performing simple optimizations). 2.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.17.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 369 unused wires. 2.17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.17.9. Finished OPT passes. (There is nothing left to do.) 2.18. Executing FSM pass (extract and optimize FSM). 2.18.1. Executing FSM_DETECT pass (finding FSMs in design). 2.18.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.18.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 369 unused wires. 2.18.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.18.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.18.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.18.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.19. Executing OPT pass (performing simple optimizations). 2.19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.19.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.19.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 26 unused cells and 369 unused wires. 2.19.5. Finished fast OPT passes. 2.20. Executing MEMORY pass. 2.20.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$techmap\FIFO_IN.$memwr$\memory$fifo.v:58$71' in module `\top': merged $dff to cell. Checking cell `$techmap\FIFO_OUT.$memwr$\memory$fifo.v:58$71' in module `\top': merged $dff to cell. Checking cell `$techmap\FIFO_IN.$memrd$\memory$fifo.v:68$68' in module `\top': no (compatible) $dff found. Checking cell `$techmap\FIFO_OUT.$memrd$\memory$fifo.v:68$68' in module `\top': no (compatible) $dff found. 2.20.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 32 unused cells and 375 unused wires. 2.20.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.20.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 32 unused cells and 375 unused wires. 2.20.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\FIFO_IN.memory' in module `\top': $techmap\FIFO_IN.$memwr$\memory$fifo.v:58$71 ($memwr) $techmap\FIFO_IN.$memrd$\memory$fifo.v:68$68 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\FIFO_OUT.memory' in module `\top': $techmap\FIFO_OUT.$memwr$\memory$fifo.v:58$71 ($memwr) $techmap\FIFO_OUT.$memrd$\memory$fifo.v:68$68 ($memrd) 2.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 32 unused cells and 375 unused wires. 2.22. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.FIFO_IN.memory: Properties: ports=2 bits=32 rports=1 wports=1 dbits=8 abits=2 words=4 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=252 dwaste=8 bwaste=4064 waste=4064 efficiency=0 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=508 dwaste=0 bwaste=4064 waste=4064 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1020 dwaste=0 bwaste=4080 waste=4080 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=2044 dwaste=0 bwaste=4088 waste=4088 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'min efficiency 2' not met. No acceptable bram resources found. Processing top.FIFO_OUT.memory: Properties: ports=2 bits=32 rports=1 wports=1 dbits=8 abits=2 words=4 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=252 dwaste=8 bwaste=4064 waste=4064 efficiency=0 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=508 dwaste=0 bwaste=4064 waste=4064 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1020 dwaste=0 bwaste=4080 waste=4080 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'min efficiency 2' not met. Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=2044 dwaste=0 bwaste=4088 waste=4088 efficiency=0 Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'min efficiency 2' not met. No acceptable bram resources found. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing ICE40_BRAMINIT pass. 2.25. Executing OPT pass (performing simple optimizations). 2.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.25.3. Executing OPT_RMDFF pass (remove dff with constant values). 2.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 32 unused cells and 383 unused wires. 2.25.5. Finished fast OPT passes. 2.26. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). Mapping memory cell \FIFO_IN.memory in module \top: created 4 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 3 $mux cells. write interface: 4 write mux blocks. Mapping memory cell \FIFO_OUT.memory in module \top: created 4 $dff cells and 0 static cells of width 8. read interface: 0 $dff and 3 $mux cells. write interface: 4 write mux blocks. 2.27. Executing OPT pass (performing simple optimizations). 2.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.27.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.27.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 2.27.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.27.6. Executing OPT_RMDFF pass (remove dff with constant values). 2.27.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 32 unused cells and 403 unused wires. 2.27.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.27.9. Finished OPT passes. (There is nothing left to do.) 2.28. Executing TECHMAP pass (map to technology primitives). 2.28.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 2.28.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 2.28.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $eqx. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $not. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $ne. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu. Using template $paramod$constmap:4b5649afbfb8c4c87464bb2a8089455e481b1596$paramod$c93dff91361b8229cab066c0b64da176df19eeef\_90_shift_shiftx for cells of type $shiftx. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $or. No more expansions possible. 2.29. Executing ICE40_OPT pass (performing simple optimizations). 2.29.1. Running ICE40 specific optimizations. 2.29.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 246 cells. 2.29.4. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 126 unused cells and 393 unused wires. 2.29.6. Rerunning OPT passes. (Removed registers in this run.) 2.29.7. Running ICE40 specific optimizations. Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$461.slice[0].carry: CO=$auto$alumacc.cc:474:replace_alu$461.BB [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[0].carry: CO=\SPI_MASTER.bitcount [0] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[10].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [10] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[11].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [11] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[12].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [12] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[13].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [13] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[14].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [14] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[15].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [15] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[16].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [16] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[17].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [17] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[18].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [18] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[19].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [19] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[20].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [20] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[21].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [21] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[22].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [22] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[23].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [23] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[24].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [24] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[25].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [25] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[26].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [26] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[27].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [27] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[28].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [28] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[29].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [29] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[30].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [30] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[5].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [5] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[6].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [6] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[7].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [7] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[8].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [8] Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$482.slice[9].carry: CO=$auto$alumacc.cc:474:replace_alu$482.C [9] Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$461.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[10].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[11].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[12].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[13].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[14].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[15].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[16].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[17].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[18].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[19].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[1].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[20].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[21].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[22].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[23].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[24].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[25].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[26].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[27].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[28].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[29].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[30].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[31].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[6].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[7].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[8].adder back to logic. Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$482.slice[9].adder back to logic. 2.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 45 cells. 2.29.10. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 126 unused cells and 502 unused wires. 2.29.12. Rerunning OPT passes. (Removed registers in this run.) 2.29.13. Running ICE40 specific optimizations. 2.29.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.16. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 126 unused cells and 502 unused wires. 2.29.18. Rerunning OPT passes. (Removed registers in this run.) 2.29.19. Running ICE40 specific optimizations. 2.29.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 2.29.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 2.29.22. Executing OPT_RMDFF pass (remove dff with constant values). 2.29.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 126 unused cells and 502 unused wires. 2.29.24. Finished OPT passes. (There is nothing left to do.) 2.30. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). 2.31. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). Selected cell types for direct conversion: $_DFF_PP1_ -> $__DFFE_PP1 $_DFF_PP0_ -> $__DFFE_PP0 $_DFF_PN1_ -> $__DFFE_PN1 $_DFF_PN0_ -> $__DFFE_PN0 $_DFF_NP1_ -> $__DFFE_NP1 $_DFF_NP0_ -> $__DFFE_NP0 $_DFF_NN1_ -> $__DFFE_NN1 $_DFF_NN0_ -> $__DFFE_NN0 $_DFF_N_ -> $_DFFE_NP_ $_DFF_P_ -> $_DFFE_PP_ Transforming FF to FF+Enable cells in module top: converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1000 to $_DFFE_PP_ for $0\pwm_on[15:0] [13] -> \pwm_on [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1001 to $_DFFE_PP_ for $0\pwm_on[15:0] [14] -> \pwm_on [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1002 to $_DFFE_PP_ for $0\pwm_on[15:0] [15] -> \pwm_on [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1003 to $_DFFE_PP_ for $0\pwm_off[15:0] [0] -> \pwm_off [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1004 to $_DFFE_PP_ for $0\pwm_off[15:0] [1] -> \pwm_off [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1005 to $_DFFE_PP_ for $0\pwm_off[15:0] [2] -> \pwm_off [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1006 to $_DFFE_PP_ for $0\pwm_off[15:0] [3] -> \pwm_off [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1007 to $_DFFE_PP_ for $0\pwm_off[15:0] [4] -> \pwm_off [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1008 to $_DFFE_PP_ for $0\pwm_off[15:0] [5] -> \pwm_off [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1009 to $_DFFE_PP_ for $0\pwm_off[15:0] [6] -> \pwm_off [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1010 to $_DFFE_PP_ for $0\pwm_off[15:0] [7] -> \pwm_off [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1011 to $_DFFE_PP_ for $0\pwm_off[15:0] [8] -> \pwm_off [8]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1012 to $_DFFE_PP_ for $0\pwm_off[15:0] [9] -> \pwm_off [9]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1013 to $_DFFE_PP_ for $0\pwm_off[15:0] [10] -> \pwm_off [10]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1014 to $_DFFE_PP_ for $0\pwm_off[15:0] [11] -> \pwm_off [11]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1015 to $_DFFE_PP_ for $0\pwm_off[15:0] [12] -> \pwm_off [12]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1016 to $_DFFE_PP_ for $0\pwm_off[15:0] [13] -> \pwm_off [13]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1017 to $_DFFE_PP_ for $0\pwm_off[15:0] [14] -> \pwm_off [14]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1018 to $_DFFE_PP_ for $0\pwm_off[15:0] [15] -> \pwm_off [15]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1021 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [0] -> \FIFO_OUT.memory[0] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1022 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [1] -> \FIFO_OUT.memory[0] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1023 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [2] -> \FIFO_OUT.memory[0] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1024 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [3] -> \FIFO_OUT.memory[0] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1025 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [4] -> \FIFO_OUT.memory[0] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1026 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [5] -> \FIFO_OUT.memory[0] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1027 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [6] -> \FIFO_OUT.memory[0] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1028 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[0][0][0]$y$565 [7] -> \FIFO_OUT.memory[0] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1159 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [0] -> \FIFO_OUT.memory[1] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1160 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [1] -> \FIFO_OUT.memory[1] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1161 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [2] -> \FIFO_OUT.memory[1] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1162 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [3] -> \FIFO_OUT.memory[1] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1163 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [4] -> \FIFO_OUT.memory[1] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1164 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [5] -> \FIFO_OUT.memory[1] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1165 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [6] -> \FIFO_OUT.memory[1] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1166 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[1][0][0]$y$573 [7] -> \FIFO_OUT.memory[1] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1344 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [0] -> \FIFO_IN.out_data_d [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1345 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [1] -> \FIFO_IN.out_data_d [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1346 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [2] -> \FIFO_IN.out_data_d [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1347 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [3] -> \FIFO_IN.out_data_d [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1348 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [4] -> \FIFO_IN.out_data_d [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1349 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [5] -> \FIFO_IN.out_data_d [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1350 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [6] -> \FIFO_IN.out_data_d [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1351 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_data_d[7:0] [7] -> \FIFO_IN.out_data_d [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1352 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_pos[1:0] [0] -> \FIFO_IN.out_pos [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1353 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\out_pos[1:0] [1] -> \FIFO_IN.out_pos [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1354 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\in_pos[1:0] [0] -> \FIFO_IN.in_pos [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1355 to $_DFFE_PP_ for $techmap\FIFO_IN.$0\in_pos[1:0] [1] -> \FIFO_IN.in_pos [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1418 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [0] -> \FIFO_OUT.memory[2] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1419 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [1] -> \FIFO_OUT.memory[2] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1420 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [2] -> \FIFO_OUT.memory[2] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1421 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [3] -> \FIFO_OUT.memory[2] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1422 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [4] -> \FIFO_OUT.memory[2] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1423 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [5] -> \FIFO_OUT.memory[2] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1424 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [6] -> \FIFO_OUT.memory[2] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1425 to $_DFFE_PP_ for $memory\FIFO_OUT.memory$wrmux[2][0][0]$y$581 [7] -> \FIFO_OUT.memory[2] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$1447 to $_DFFE_PP_ for $techmap\SPI_MASTER.$0\clockphase[0:0] -> \SPI_MASTER.clockphase. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2299 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [0] -> \FIFO_IN.memory[1] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2300 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [1] -> \FIFO_IN.memory[1] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2301 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [2] -> \FIFO_IN.memory[1] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2302 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [3] -> \FIFO_IN.memory[1] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2303 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [4] -> \FIFO_IN.memory[1] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2304 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [5] -> \FIFO_IN.memory[1] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2305 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [6] -> \FIFO_IN.memory[1] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2306 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[1][0][0]$y$524 [7] -> \FIFO_IN.memory[1] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2310 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [0] -> \FIFO_OUT.out_data_d [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2311 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [1] -> \FIFO_OUT.out_data_d [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2312 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [2] -> \FIFO_OUT.out_data_d [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2313 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [3] -> \FIFO_OUT.out_data_d [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2314 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [4] -> \FIFO_OUT.out_data_d [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2315 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [5] -> \FIFO_OUT.out_data_d [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2316 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [6] -> \FIFO_OUT.out_data_d [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2317 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_data_d[7:0] [7] -> \FIFO_OUT.out_data_d [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2318 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_pos[1:0] [0] -> \FIFO_OUT.out_pos [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2319 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\out_pos[1:0] [1] -> \FIFO_OUT.out_pos [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2320 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\in_pos[1:0] [0] -> \FIFO_OUT.in_pos [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2321 to $_DFFE_PP_ for $techmap\FIFO_OUT.$0\in_pos[1:0] [1] -> \FIFO_OUT.in_pos [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2338 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [0] -> \FIFO_IN.memory[3] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2339 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [1] -> \FIFO_IN.memory[3] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2340 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [2] -> \FIFO_IN.memory[3] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2341 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [3] -> \FIFO_IN.memory[3] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2342 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [4] -> \FIFO_IN.memory[3] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2343 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [5] -> \FIFO_IN.memory[3] [5]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2344 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [6] -> \FIFO_IN.memory[3] [6]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$2345 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[3][0][0]$y$538 [7] -> \FIFO_IN.memory[3] [7]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$683 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[2][0][0]$y$532 [0] -> \FIFO_IN.memory[2] [0]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$684 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[2][0][0]$y$532 [1] -> \FIFO_IN.memory[2] [1]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$685 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[2][0][0]$y$532 [2] -> \FIFO_IN.memory[2] [2]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$686 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[2][0][0]$y$532 [3] -> \FIFO_IN.memory[2] [3]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$687 to $_DFFE_PP_ for $memory\FIFO_IN.memory$wrmux[2][0][0]$y$532 [4] -> \FIFO_IN.memory[2] [4]. converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_df